Computer Architecture and Organization - 4

Aim: To implement various 4-bit arithmetic Micro-operations           using arithmetic unit.

 

Theory

Arithmetic micro operation of the form L:  R _A  (R_A + R_B) refers to two data items contained in R_A and R _B input to a parallel adder with the result being stored back in R _A (Fig.). Loading     of the result in R_A is subject to the availability  of the control  signal designated as L  (that  is  load control of R _A) . Note that adder being a combinational logic, the adder output is available after a delay of the associated combinational circuit. Input to adder may be also controlled by providing AND word gates on the data paths from R _A and R _B to the adder under the control signal C (Fig.). the control signals `C' and 2's complement are at logic `0' for add operation.

 

The subtract micro operation L:  R _A  (R _A - R_B) in 2's complement arithmetic has    the form L_A : R_A <--  R_A  + R_B + 1 where R_B is 1's complement of R _B  the hardware  implementing both  Add/Subtract  operation  is  shown  in   Fig.   Where   the   control   signals `C' and 2's complement are at logic `1' for subtract operation and `0' for add operation. The EX-OR word gate inverts the content of R _B for C = 1 which also makes input carry C _O =             1  to  make  2's complement of R_B circuit in Fig. is so designed that it can support both 1's and   2's complement of R_B as input to the adder.

The other common arithmetic micro operations are increment, decrement,  1’s  complement, 2's complement etc. Each of these operations  can be implemented with the help    of multiple micro operations on the structure of Fig.

Prepare a table for above operations and write micro operation and control  signal for  given fig.

For Example:

Operation	Microoperation	Control signal
Increment	R B  1	1.Set R B to 1
	R A  RA + RB	2.Set C to 0
		3. L A at RA

Circuit Diagram:

TABLE: MICROOPERATION

Operation	RA0	RA1	RA2	RA3	RB0	RB1	RB2	RB3	C	2’S
ADD RA,RB	0	1	0	1	1	0	1	0	0	0
SUBTRACTION RA, RB	0	1	0	1	1	0	1	0	1	1
INCREMENT RA	0	1	0	1	0	0	0	0	0	1
DECREMENT RA	0	1	0	1	0	0	0	0	1	0
INCREMENT RB	0	0	0	0	1	0	1	0	0	1
DECREMENT RB	0	0	0	0	1	0	1	0
1’S COMPLEMENT RA	0	1	0	1	0	0	0	0
2’S COMPLEMENT RA	0	1	0	1	0	0	0	0
1’S COMPLEMENT RB	0	0	0	0	1	0	1	0	1	0
2’S COMPLEMENT RB	0	0	0	0	1	0	1	0	1	1
TRANSFER A0	1	0	1		0	0	0	0	0	0
TRANSFER B0	0	0	0		1	0	1	0	0	0

 

Circuit